1. Field of the Invention
The present invention relates to the field of analog-to-digital (A/D) converters. More particularly, the present invention relates to a digitally self-calibrating A/D algorithmic converter architecture including pipeline architecture that functions both as an A/D and a D/A converter.
2. Description of the Related Art
Analog to digital converters with pipeline architecture are well suited for low-power, high speed applications. Among the several of the currently used high conversion speed techniques such as flash, multi-step, pipeline, interpolating, and time-interleaved successive approximation, the pipeline technique offers the best trade-off between minimizing circuit complexity, silicon area, and power consumption with respect to conversion speed. The pipeline architecture can generally provide high throughput rates and occupy small die areas which are both desirable and cost efficient in A/D converters. These advantages result from the concurrent operation of each of the multiple stages in the pipeline architecture.
Broadly speaking, at any given time during the operation of the pipeline A/D converter, the first stage operates on the most recent sample inputted while subsequent stages in the pipeline architecture concurrently operate on residues from the previous samples outputted from prior stages of the cascaded pipeline architecture.
A typical M-bit/stage pipeline A/D converter consists of N, M-bit/stages, where N represents the number of stages in the pipeline architecture, and further, where N*M=K. For example, a pipeline A/D converter architecture made up of five stages (N=5) with each stage producing 2 bits (M=2) will result in a 10 bit A/D converter (K=10).
FIG. 1 shows the general architecture of a K-bit pipeline A/D converter. At stage i, the analog input Vresi (the residue from the previous stage) is converted into a digital representation D.sub.i with an A/D subconverter and the analog residue Vres.sub.i-1, is computed and passed to the next stage (i-1). In other words, the analog input is sampled and held at a sample and hold circuit 101. The result is converted to an M-bit digital code D.sub.i by an analog to digital subconverter 102. The first stage of the pipeline architecture produces an M-bit representation D.sub.N which are the most significant bits (MSB) of the final digital output. Then, this M-bit digital code D.sub.N is used by a local digital to analog converter 103 to create an analog equivalent of the M-bit digital code D.sub.N. This analog equivalent Vdac.sub.i is subtracted from the output of the sample and hold circuit 101 to produce an analog residue. The resulting analog residue is subsequently amplified by an amplification factor of 2.sup.M by an amplifier 104 and sent to the next stage (i-1) of the pipeline architecture as the input signal Vres.sub.i-1 of the subsequent (i-1)th stage. The residue signal Vres.sub.i-1 can be calculated by the following expression. EQU Vres.sub.i-1 =2.sup.M *(Vres.sub.i -Vdac.sub.i) (1)
for i=n, . . . , 1. As can be seen from equation (1), because the residue at each stage is multiplied by 2.sup.M, each successive stage has the same range of input voltages rather than having that range geometrically decreasing toward zero. If the local D/A converter in each stage is linear, the D/A converter output Vdac.sub.i at each stage i can be represented by the following expression. EQU Vdac.sub.i =D.sub.i *2.sup.-M *Vref (2)
Where Vref is the reference signal applied uniformly to each stage of the pipeline architecture. The multiplied factor (D.sub.i *2.sup.-M) then represents a fraction of the reference signal Vref which has already been encoded and is to be subtracted from the analog remainder Vres.sub.i.
If M=1, (i.e., each stage produces 1 bit) the D/A converter in each stage only has two possible output signal levels. Then, this D/A conversion will always be linear. This 1-bit/stage implementation is very attractive since the A/D subconverter can be implemented with a simple comparator. Given the inherent linearity of the D/A converter, the overall linearity of the A/D converter will be determined only by the comparator offsets and the stage gain errors. For such conversion stage having a nominal gain of 2, equations (1) and (2) can be simplified to the following residue expression. EQU Vres.sub.i-1 =2.multidot.Vres.sub.i -D.sub.i .multidot.Vref(3)
In an ideal case, the digital representation of an input voltage V.sub.IN for the A/D converter is given by the following expression. ##EQU1## For example, in a case where N=5, Equation (4) approximates to Vref*(1/2+1/4+1/8+1/16+1/32), or Vref*(31/32). The digital representation of the input voltage V.sub.IN is then "11111" corresponding to D.sub.5, D.sub.4, D.sub.3, D.sub.2, D.sub.1.
The digital code D.sub.i of each stage in equation (4) can take one of two values: 0 or +1. For the input residue signal Vres.sub.i larger than Vref/2, the digital output code D.sub.i is +1. For the input residue signal Vres.sub.i less than Vref/2, the digital output code D.sub.i is 0. This can be achieved by a simple circuit as shown in FIG. 2 illustrating a switched capacitor circuit implementing Equation (1). The switching arrows for switches S.sub.1 -S.sub.5 indicate a "sample" and a "hold" phases for the 1-bit per stage analog residue computation circuit.
FIG. 3A illustrates the sample phase of FIG. 2 where switches S.sub.1, S.sub.3, and S.sub.4 are closed while switches S.sub.2 and S.sub.5 are open. This switching configuration ensures that the i-th stage input signal Vres.sub.i is sampled across capacitors C.sub.1 and C.sub.2 thereby charging both capacitors to a voltage of Vres.sub.i-1. Then, the capacitor stored voltage Vres.sub.i-1, is compared with Vref/2 producing the digital output code D.sub.i.
FIG. 3B illustrates the hold phase of the circuit in FIG. 2 where switches S.sub.2 and S.sub.5 are closed while switches S.sub.1, S.sub.3, and S.sub.4 are open. This switching configuration couples capacitor C.sub.2 to D.sub.i *Vref, while capacitor C.sub.1 is connected to the output of the operational amplifier 201. If capacitors C.sub.1 and C.sub.2 are assumed to have equal capacitances, this connection ensures that the output of the operational amplifier Vres.sub.i-1 is equal to the desired residue as according to equation (3).
In practice, mismatches in the capacitors C.sub.1 and C.sub.2 and charge injection from switch S.sub.1 introduce errors in the transfer characteristic and linearity errors in the digital representation. These errors can be compensated with a digital self-calibration and digital correction techniques.
Conventional self-calibration and digital correction techniques are discussed in S. H. Lee et al., "Digital-Domain Calibration of Multistep Analog-to-Digital Converters", IEEE J. Solid-State Circuits, vol. 27, No. 12 at pp. 1679-1688, December 1992, and in A. Karanicolas et al., "A 15-b 1M-sample/s Digitally Self-Calibrated Pipeline ADC", IEEE J. Solid-State Circuits, vol. 28, No.12 at pp. 1207-1215, December 1993. According to these calibration methods, each transition is calibrated starting with the lower significant bits, i.e., the least significant bit (LSB), and then advancing toward the most significant bit (MSB). Correction coefficients are stored in memory locations mem.sub.i associated with each digital data bit D.sub.i.
The final input digital conversion code (C.sub.DS) is then obtained from the following expression. ##EQU2## Where Offset is the overall signal offset of the entire pipeline architecture.
Additionally, in order for the digital correction to work according to the above conventional approaches, some redundancy needs to be introduced in the system, either using reduced gain stages or residue overflow reduction stages. Furthermore, the conversion from the input digital code C.sub.DI to the corresponding digital bit representation D.sub.i (for i=1, . . . N) adds to the latency, but usually this latency is not a major concern in an algorithmic (cyclic or pipeline) converter.
FIG. 4 illustrates a conventional digital self-calibrated A/D pipeline converter with reduced gain stages. As shown, stages 401 are set with nominal gains of less than 2 while stages 402 are set to nominal gains of 2. The calibration by a digital calibration/correction logic 403 starts at the stage 401 with the nominal gain of less than 2 constituting the least significant bit (for example, stage (i-1)), and continues through to stage (i). Additionally, the digital calibration/correction logic 403 generates correction coefficients CC.sub.i for each stage (1) through (i) of the converter. The value of the reduced gain is selected to ensure sufficient gain reduction such that the residue at from each stage never exceeds the reference boundary in the worst case when the maximum capacitor mismatch, comparator offset, and charge injection error magnitudes compound. In other words, it is crucial to use a nominal gain of less than 2 such that the output of each stage never exceeds the boundaries of set by the upper and lower reference voltages.
FIG. 5 illustrates a self-calibrating pipeline A/D converter architecture with residue overflow stages as discussed in co-pending, commonly assigned patent application Ser. No. 08/337,253, filed Nov. 10, 1994, and entitled "Radix 2 Architecture and Calibration Technique for Pipeline Analog to Digital Converters," the disclosure of which is incorporated herein by reference. In this approach, an overflow reduction stage 502 is placed at a predetermined interval between the other stages 501 of the pipeline architecture such that overflow errors occurring in the manufacturing process used for producing the converter are compensated. Again, a digital calibration/correction logic 503 generates correction coefficients CC.sub.i corresponding to each stage (from (1) to (i)) of the converter architecture. The exact sequence of the overflow stages is not critical as long as there are enough to avoid the aforementioned problem. The overflow reduction calibration logic 502 operates in a similar manner to the digital calibration logic 501 except that in the overflow reduction calibration logic 502, upper and lower correction coefficients CC.sub.i-2(L) and CC.sub.i-2(H) are used to maintain the calibration within the operable range.
As a matter of design, however, it is desirable to place the overflow reduction stages in the converter to avoid the possibility of any out of range input multiplying enough to reach the power supply voltage before that residue is brought back into the appropriate input range by an overflow reduction stage. This can be achieved by assuming the worst case overflow for a stage and ascertaining the maximum out of range of any stage operation before the output becomes non-linear.
All of the above-mentioned approaches were previously limited to analog to digital converters. To convert a digitized signal into analog form requires, under the conventional approach, added circuitry which necessarily entails added complexity, component matching problems, and higher manufacturing cost.
Component matching is of particular importance because matched characteristics of the elements in the converter determine the converter's attainable accuracy. Conventional devices that require separate architectures for both A/D conversion and D/A conversion will include added complexity as compared to architectures designed solely for A/D conversion or D/A conversion.
To minimize the number of necessary steps for conversion, it would be desirable to have a pipeline A/D converter architecture which uses the same correction coefficients during the A/D and D/A conversions. Therefore, given the advantages of a pipeline structure for A/D converters outlined above, it would be desirable to have a self-calibrating reversible pipeline A/D and D/A converter architecture which performs A/D and D/A conversions using the same architecture and the same calibrating variables.